FIG. 4 is a circuit diagram illustrating an operational amplifier according to the related art (for example, see Japanese Patent Application Laid-Open Publication No. 11-154832).
As illustrated in FIG. 4, transistors Tr1 and Tr2 make up a current mirror circuit. The transistor Tr2 provided on the output side of the current mirror circuit operates as a constant current source. That is, the transistor Tr2 passes a drain current that has substantially the same value as the value of a current that flows through a first current source 1.
The drain of the transistor Tr2 is coupled to the sources of transistors Tr3 and Tr4. The drain of the transistor Tr3 is coupled to the drain of a transistor Tr5, the gate of the transistor Tr5, and the gate of a transistor Tr6. The source of the transistor Tr5 is coupled to a ground GND. The drain of the transistor Tr4 is coupled to the drain of the transistor Tr6. The source of the transistor Tr6 is coupled to the ground GND. An input signal VM is applied to the gate of the transistor Tr3. An input signal VP is applied to the gate of the transistor Tr4. The transistors Tr2 to Tr6 are included in a differential input circuit activated based on the constant current supplied from the transistor Tr2.
A coupling point of the drains of the transistors Tr3 and Tr5, that is, a node N1, is coupled to the gate of a transistor Tr11. A coupling point of the drains of the transistors Tr4 and Tr6, that is, a node N2, is coupled to the gate of a transistor Tr12. The sources of the transistors Tr11 and Tr12 are coupled to the ground GND through a second current source 2.
The drain of the transistor Tr11 is coupled to the drain of a transistor Tr13. The source of the transistor Tr13 is coupled to a power source Vcc. The drain of the transistor Trig is coupled to the drain of a transistor Tr14, and the gates of the transistors Tr13 and Tr14. The source of the transistor Tr14 is coupled to the power source Vcc. The transistors Tr11 to Tr14 and the second current source 2 are included in a differential amplifier circuit that amplifies a differential voltage between the node N1 and the node N2.
A coupling point of the drains of the transistors Tr11 and Tr13, that is, a node N3, is coupled to the gate of an output transistor Tr21. The source of the transistor Tr21 is coupled to the power source Vcc. The drain of the transistor Tr21 is coupled to an output terminal To.
The node N2 is coupled to the gate of an output transistor Tr22. The drain of the transistor Tr22 is coupled to the output terminal To, and the source of the transistor Tr22 is coupled to the ground GND. An output signal Vout is applied to the gate of the transistor Tr3 as the input signal VM.
For example, when the voltage value of the input signal VP becomes higher than the voltage value of the input signal VM (the output signal Vout), the value of the drain current of the transistor Tr4 decreases and becomes lower than the value of the drain current of the transistor Tr3. As a result, the voltage level of the node N2 falls and the transistor Tr22 is turned off.
When the potential of the node N2 becomes lower than the potential of the node N1, the potential of the node N3 decreases based on an operation of the differential amplifier circuit. When the potential of the node N3 decreases, the output transistor Tr21 is turned on and the voltage level of the output signal Vout rises. As a result, the voltage values of the input signal VP and the output signal Vout (the input signal VM) become substantially the same.
As the potential of the node N3 decreases, the drain current supplied from the transistor Tr21 to the transistor Tr22 increases. When the drain current of the transistor Tr22 increases, the value of a voltage between the gate and the source (hereinafter referred to as a “gate-source voltage”) of the transistor Tr22 increases. As a result, the potential of the node N2 increases. The potentials of the nodes N1 and N2 become substantially the same by controlling the drain current of the transistor Tr21 based on the differential voltage between the nodes N1 and N2. When the potentials of the nodes N1 and N2 are substantially the same, the drain voltages of the transistors Tr3 and Tr4 are substantially the same. Accordingly, a voltage between the source and the drain (hereinafter referred to as the “source-drain voltage”) of the transistor Tr3 and the source-drain voltage of the transistor Tr4 become substantially the same, and the drain currents of the transistor Tr3 and Tr4 become substantially the same. As a result, the gate-source voltages of the transistors Tr3 and Tr4 may be substantially the same, and generation of an offset voltage of the input signal VP and the output signal Vout may be reduced if not prevented.